1. Technical Field
This disclosure generally relates to frequency synthesizers. More specifically, this disclosure relates to highly flexible fractional N frequency synthesizers.
2. Related Art
Many applications in modern high-speed communication systems have a baud rate that is a non-integer multiple of the reference clock frequency. For example, in a USB 3.0-based system, the baud rate can be 5 Gbps and the reference clock frequency can be 19.2 MHz, resulting in a non-integer relationship between the baud rate and the clock frequency.
Conventional fractional N frequency synthesizers have a number of drawbacks. Some conventional synthesizers are designed to generate a specific fractional N frequency, i.e., the synthesizer is not programmable. Others are limited in the number of fractional frequencies that can be generated. In addition, because of the way they work, some fractional N frequency synthesizers introduce jitter and/or frequency spurs in the output clock signal, and/or they may change the duty cycle of the clock pulses. These drawbacks can be a serious problem because high-speed interfaces often need to operate at multiple frequencies, and communication standards often impose stringent timing requirements, such as low jitter and a 50/50 duty cycle, on their clocks.